Multi-channel analog multiplier and systems

ABSTRACT

A single analog multiplier is used to obtain the products of many pairs of analog signals. The many pairs of analog signals are connected to the multiplier on a time-sharing basis by cyclically sampling the analog signals and applying them in repetitive sequence to the analog multiplier. Conventional multiplexing techniques are used for this purpose. The successive output signals of the multiplier are then demultiplexed and the amplitudes of the product signals are separately stored to provide the system output. The accuracy of the multiplication is constrained to be very high by repetitively correcting the output of the multiplier according to the product obtained from one or more pairs of analog signals whose products should be fixed and are known references. By suitably operating upon the multiplier outputs, many additional functions such as scaling, filtering, square root extraction, division, etc. may be obtained.

United States Patent 1 Dickman et al.

[ 51 Apr. 17, 1973 [5 MULTl-CHANNEL ANALOG 3,624,368 11/1971 Close ...235/150.51 MULTIPLIER AND SYSTEMS 3,632,888 l/l972 Glaser ..l78/5O X [75] Inventors: Allen C. Dickman, North Tonawan- Primary Examiner-JoSePh F gg da; Theodore Roess; George Attorney-John B. Bean et al. Mathewson, both of Williamsville, all Of 5 71 ABSTRACT [73] Asslgnee: Textron Provldence A single analog multiplier is used to obtain the [22] Filed: Aug. 19, 1971 products of many pairs of analog signals. The many pairs of analog signals are connected to the multiplier [21] l73ll9 on a time-sharing basis by cyclically sampling the analog signals and applying them in repetitive [52] US. Cl. ..235/194, 235/ 150.52, 318/562 sequence to the analog multiplier. Conventional mul- [51] Int. Cl. ..G06g 7/16, G06j l/OO tiplexing techniques are used for this purpose. The [58] Field of Search ..235/ 194, 150.52, successive output signals of the multiplier are then 235/1505], 150.5; 318/562; 328/151; demultiplexed and the amplitudes of the product 340/347 D-347 A, 347 CC, 347 SH; 179/ 15 signals are separately stored to provide the system out- R, 15 AB, 15 A, 15 AW; 178/50, DIG. 23 put. The accuracy of the multiplication is constrained to be very high by repetitively correcting the output of [56] References Cited the multiplier according to the product obtained from one or more pairs of analog signals whose products UNITED STATES PATENTS should be fixed and are known references. By suitably 3,610,896 10 1971 Heid ..235/l50.5 operating p the multiplier u p y addi- 2,6l0,9l0 10/ 1971 Udall... ..235/l94 tional functions such as scaling, filtering, square root 3,059,228 10/ 1962 Beck et al.. ....340/347 SH extraction, division, etc. may be obtained. 3,573,442 4/197] Andeen ....235/l50.5l X 3,582,628 6/1971 Brussolo ..235/ 150.51 X 11 Claims, 14 Drawing Figures 56\ 4O l I i SAllll LE 48 QDNPEN S A T E 10 l AND 1 IN l6 g HOLD 22 l 30 32 42 coNLPENsAT|Ne OUTPUTS g l l SAMPLE 5 ANALOG DATA 5 l AND 44 'NPUTS 2 l HOLD so SAMPLE 52 ANALOG myi A QEB MULTIPLIER 8 g 3e 5 DATA" Ll-l 1 Z I .8 28 Q NAN; M E {in l L A 1 r' y l E HOLD, 54

,2 5 24 38 2 v 46 E yl ANALOG DATA 5 g y INPUTS g 2 PIIENIEU H 3.728.535

SHEET 0% 0F 12 INPUT CONTROL LOGIC MU LTIPLEXER OUTPUT CONTROL LOGIC 'INVENTOIIQS.

ALL N c. DICKMAN GEORGE R MATHEWSON 4 THEODORE L. ROESS BY n Zea...

ATTORNEYS.

PATENTED 1 New 3, 7 28.535

I SHEET 05 HF T2 INPUT CONTROL LOGIC I MULTIPLEXER OUT PUT CONTROL LOGIC INVENTORS ALLEN C. DlCKMAN GEORGE R. MATHEWSON FIG. 5 THEODORE L. ROESS BY zaw/ EBA.-

ATTORNEYS.

" PATENTEDAPR 1 1191s SHEET 0s 0F 12 INVENTORS. ALLEN C DICKMAN GEORGE R. MATHEWSON THEODORE L. ROESS ATTORNEYS INVENTORS. ALLEN c DICKMAN "GEORGE R. MATHEWSOI THEODORE L. ROESS ATTORNEYS PATENTED APR 1 "H975 SHEET 07 0F 12 PATENTEB APR! 7 I973 SHEET 09 0F 12 mum INVENTORS.

ALLEN C. DICKMAN GEORGE R MATHEWSOF BY THEODORE L. ROESS ATTORNEYS MULTI-CHANNEL ANALOG MULTIPLIER AND SYSTEMS BACKGROUND OF THE INVENTION Many control systems require accurate real time multiplication and may involve the need for such accurate multiplication with respect to many pairs of analog signals. If this requirement is met in any such system by employing an accurate multiplier for each pair of signals to be processed, excessive packaging volume and increased expense due to handling and testing of individual multipliers results.

Moreover, there is a need to fill the gap between conventional analog computing systems and digital computing systems. In many areas of signal processing, neither purely analog computing techniques nor purely digital computing techniques represent the most efficacious manner of handling and operating upon the signals involved and it would be advantageous to utilize mutually exclusive characteristics of these two basic systems.

BRIEF SUMMARY OF THE INVENTION From the broadest standpoint, the present invention relates to the concept of utilizing existing analog multipliers in hybrid fashion in which a number of analog signal pairs are sampled sequentially at a selected rate with each pair of the resultant sample signals being channeled through a common analog multiplier. The analog signal pairs are non-sinusoidal voltage signals of bounded amplitude and of bounded amplitude rate of change, which bounds allow the multiplier to respond accurately at the sampling rate involved.

The sampling rate may also be used advantageously to demodulate in such fashion as requires less filtering since no second harmonics are generated as in normal demodulation of an amplitude modulated signal. Thus, if a number of signals which are amplitude modulated at some carrier frequency are sampled at a rate corresponding to and synchronized with the carrier frequency, demodulation at the carrier frequency may be effected, with the above advantage, by applying one of the modulated signals to the x or y input channel while applying a reference signal to the other input channel with such other signal being controlled in amplitude by a dc reference voltage to permit the multiplier channel gain to be programmed between 0 and 1.0. The sampling interval occurs at a constant discrete time increment with respect to the synchronized sample rate which specifies the limit of the carrier quadrature component so as not to exceed the allowable quadrature error.

The present invention is specifically directed to a multichannel, four quadrant analog multiplier system which provides high accuracy over a wide range of ambient temperatures.

According to one aspect of the present invention, a pulse area modulated, four quadrant single channel analog multiplier is used on a time-sharing basis in conjunction with a large number of analog signal pairs which are to be processed. At least one pair of fixed input analog signals whose product should therefore be a fixed reference is included in the time-sharing input to the multiplier and deviations of the multiplier output from this reference product are used repetitively and continuously to update the accuracy of the multiplier.

Specifically, a multi-channel system of the type described has been developed which exhibits an accuracy of 0.2 percent over the temperature range of 40 to C. The system may be integrated easily into existing systems and displays excellent flexibility and maintainability with maximum packaging density.

The updating of the accuracy of a wide band width low accuracy multiplier may be effected through the use of several reference channels to accommodate for any inaccuracies which might prevail. It has been found that the presently available pulse area analog multipliers may be made very accurate by updating for offset correction and scale factor correction along. The offset correction accommodates for initial offset and offset voltage change and the scale factor corrections accommodate for gain change both of which are due to ambient temperature variation of the electrical components of the multiplier channel.

BRIEF DESCRIPTION OF THE DRAWING FIGURES FIG. 1 is a block diagram illustrating certain principles of the present invention;

FIGS. 2-5 illustrate a complete system according to a preferred embodiment of the invention;

FIG. 6 is a circuit diagram, partly symbolic, illustrating the multiplier channel and the scale factor and offset compensation circuits;

FIG. 7 is a circuit diagram illustrating the phase lock, frequency divider and certain timing control circuits of a preferred embodiment;

FIGS. 8-10 are timing diagrams illustrating certain principles of the invention;

FIG. 1 1 is a block diagram of a modification;

FIG. 12 is a block diagram illustrating a method of modulating according to this invention;

FIG. 13 is a diagram illustrating the modulating principles of FIG. 12 applied to the system of FIG. 1; and

FIG. 14 illustrates a specific application of the present invention, showing a programmed computation application.

DETAILED DESCRIPTION OF THE INVENTION With reference now more particularly to FIG. 1, two sets of analog signal inputs are applied to the multiplexing circuits l0 and 12, each of the multiplexing units receiving an identical number of inputs which, in the instance shown, consist of a number n of inputs in each case. Certain of the inputs in each case are designated as compensating inputs such as the inputs 14 and 16 for the x inputs to the unit 10 and the inputs l8 and 20 for the y inputs to the unit 12. A clock 22 is connected to both of the units 10 and 12 so that sample signals indicative of the analog amplitudes of the two sets of signals appear at the respective conductors 22 and 24. designated as the x, and y, outputs of the multiplexing circuits 10 and 12 respectively, These outputs are applied on a time-sharing basis to the analog multiplier means indicated generally by the reference character 26 by means of the two conductors 22 and 24 connected to the input terminals thereof. The output terminal 28 of the multiplexer 26 is applied to a demultiplexing circuit indicated generally by the reference character 30 which has a number of discrete output terminals 32, 34 and 36, 38 corresponding to the products of the sample signal pairs applied as inputs sequentially number n of inputs to each of the multiplexing units and 12.

Sample and hold circuits such as those indicated at 44 and 46 are connected to each of the discrete output terminals of the demultiplexing circuit 30 (i.e. at 36 and 38) at which the data product outputs appear. For the compensating product outputs as at 32 and 34, either sample and hold circuits 40 and 42 or integrate and hold circuits are used, dependent upon the nature of the compensation as will hereinafter appear.

The outputs of those sample and hold circuits corresponding to the products of pairs of x and y compensating inputs to the multiplexing circuits l0 and 12 are connected to the multiplier 26 to compensate drift due to temperature instability thereof. In FIG. 1, this is illustrated diagrammatically by the dashed line 56.

In this fashion, error sources within the multiplier 26 which are temperature dependent may be minimized. The number of compensating channels employed for this purpose may vary according to the practical requirements encountered. For example, size compensating channels may be employed, three of which are used to compensate for errors tending to cause deviation from the zero output, two of which are used to compensate for errors in scale factor, and one of which is sued to assure linearity. Thus, for the first three compensating channels mentioned, the three x, y conditions x=+V,y=0;x=0, y=+V; and x=0,y=0 where +V is an arbitrary reference voltage, should yield zero output from the multiplier in each case. Deviations from zero output in each case are fed back from the appropriate integrate and hold circuits to adjust the appropriate bias inputs to the multiplier to achieve the zero output. Scale factor compensation may be achieved by the next two channels. For example, if k=a and the limits of the multiplier output are volts, with a and b being related such that ab =b(i.e. k=0.l and b=il0 bolts), the equation kxm 12 should equal zero for the two conditions x;=+b, y 'i-b and x;= b, y +b. Obviously, suitabIe summing circuits are required to implement the two correction channels necessary to provide the proper biases to compensate for scale factor error. The last channel mentioned may achieve linearity compensation in a particular quadrant pair by replacing the x =0, y=+V bias with the correction term necessary to minimize the different in the absolute values of the preset positive and negative outputs of the multiplier means (i.e. i b volts). Thus, the product kx y, where x;= b and y, b may be used for this purpose.

The FIGS 2-5 inclusive illustrate, in block diagram form, a preferred embodiment of the present invention. Referring first to FIG. 4, an input control logic circuit is indicated generally by the reference character 60 and has, as x inputs thereto, the input conductors 62-90 and the 15 y input conductors 92-120. The x output of the circuit 60 is at the conductor 122 whereas the y output is at the conductor 124. These two outputs are applied, over the conductors 126 and 128 respectively shown in FIG. 3, to the respective buffer amplifiers 130 and 132 whose outputs at the conductors 134 and 136 are adjustable by means of the variable resistance elements 138 and 140 respectively. These two output conductors 134 and 136 are, as is shown in FIG. 2, applied to the analog multiplier 138 whose output is applied over the conductor 140 to the scale factor amplifiers 142 and 144 as is shown in FIG. 3 through a manually set variable resistance 146 and a compensating variable resistor 148 whose purpose will be presently apparent. The signal appearing, then, at the conductor 150 is proportional to the product of the pairs of x and y signals having their input to the control circuit 60 and this signal is applied over the conductor 152 both to the output control logic circuit 154 shown in FIG. 4 and to the output control logic circuit 156 shown in FIG. 5. The signal is also applied to the output compensation control logic circuit 156 shown in FIG. 2.

The system shown in FIGS. 2-5 is connected to accommodate for 30 pairs of x and y inputs analog data signals but, with the circuitry shown, the system is capable of expansion to accommodate 64 input signals pairs. As shown in FIG. 4, the input control logic circuit 60 has 15 x input conductors 62-90 and 15 y input conductors 92-120. Similarly, the input control logic circuit 158 of FIG. 5 has 15 x inputs at the conductors 160-188 and 15 y input conductors -218. Likewise, the input control logic circuit 158 has respective x and y outputs at the conductors 220 and 222 which are connected with the output conductors 122 and 124 of the circuit 60 as shown in FIG. 4 for common connection to the input signal conductors 126 and 128 which connect to conductors 134 and 136 through buffers 130 and 132, then on to the multiplier circuit 138 as shown in FIGS. 3 and 2 respectively. These conductors 220 and 222 also extend to the input compen- I sation control logic circuitry 224 such that the respective x and y outputs at 226 and 228 thereof may be applied to multiplier circuitry 138 at the proper time as will be hereinafter described.

Referring again to FIGS. 4 and 5, the respective output logic control circuits 154 and 156 each have 15 output signals appearing at the respective conductors 230-258 and 260-288 which are the output signals of interest. It will be appreciated that the output signals occur sequentially from the output conductor 230 through the output conductor 288, multiplexing of the x and y signals being effected by the input control logic circuit 60 and 158 under control of the respective multiplexing circuits 290 and 292 and demultiplexing of the output signals being effected by the circuits 154 and 156 under the control of the respective circuits 290 and 292. Each of the product output signals is sampled and held so as to produce stepped output signals which are the individual signals of interest.

The circuitry 290 has outputs sequentially at the conductors t -t whereas the circuitry 292 has a sequential output conductors t -t it being understood that the subscripts relate to sequential time steps. The conductors 300, 302, 304, 306, 308, 310 and 312-are connected to the output conductors t -t of the circuit 290 whereas the conductors 314, 316, 318, 320, 322, 324, 326 and 328 are connected the respective conductors t t and are connected both to the input control logic circuitry 60 and to the output control logic circuitry 154. Similarly, the output conductors t -t of the circuitry 292 (FIG. 5) are connected to the respective conductors 330, 332, 334, 336, 338, 340 and 342 whereas the output conductors t -t are connected to the respective conductors 344, 346, 348, 350, 352, 354, 356 and 358. The output conductor t, of the circuitry 290 in FIG. 4 and the output conductor of the circuit 292 in FIG. 5 and whichcorrespond respectively to the seventh and twenty-third time slots, are connected respectively to the input and output compensation control logic circuit conductors 360 and 362 as shown in FIG. 2 thus, there are gaps in the outputs of the circuits 154 and 156 at the seventh and twentythird time slots of each sequence of output signals therefrom. The sequencing of the systems of FIGS. 4 and 5 are effected by the control gates 364 and 366 associated with the respective circuits 290 and 292 and with the control 364 having a select input 368 and an inhibit input 370 whereas the control gate 366 has a select input at the conductor 372 and an inhibit input at the conductor 374, the corresponding signals occurring thereat being described hereinafter.

The product signal outputs corresponding to the seventh and twenty-third time slots appear at the output conductors 376 and 378 in FIG. 2 and are those which are used for compensation to provide for the temperature stability inherent in the system. To the input compensation control logic circuit 224, corresponding to the seventh time slot, there is a reference zero voltage input at the conductor 380 and at the input conductor 382 thereof, there also appears this zero reference voltage, the product of which is applied, during the seventh time slot, over the conductor 376 to the offset compensation amplifier 384 of FIG. 3. The amplifier 384 is a differential amplifier connected to perform an electrical integration on the input signal and deviations of the signal at the conductor 376 from a zero reference appear as an output at the conductor 386 of the integrator amplifier 384 which is applied as shown in FIG. 2, as a biased offset voltage compensation signal to the multiplier circuit 138.

During the twenty-third time slot, a minus reference voltage input at the conductor 388 in FIG. 2 and a plus reference voltage input at the conductor 390 are controlled, by the logic control input conductor 362 to produce a signal proportional to their product at the conductor 378. This signal is applied (FIG. 3) to a sample and hold circuit 392 and then to the scale factor compensation amplifier integrator 394 whose output at 396 is used to effect adjustment of the variable resistor element 148 thereby affecting the amplifiers 142 and 144 to provide a scale factor corrected output at the conductor 150.

The amplifiers 400 and 402 shown in FIG. 3 provide the respective plus and minus voltage reference signals at the previously mentioned conductors 388 and 390 and this plus voltage reference is also applied over the conductor 404 through the summing resistor 406 as an input to the amplifier 394. With this configuration, the plus reference signal at the conductor 404 is summed with the signal proportional to the product of the plus and minus voltage references as applied through the summing resistor 408 from the sample and hold ampli fier 392. This, if the plus and minus reference voltages are, for example, volts in each instance there should be a zero input to the amplifier integrator 394 during the twenty-third time slot such that deviation from this input as reflected by the output of the amplifier integrator 394 will effect the requisite variation of the resistor element 148 whereby to correct the scale factor and render the system stable.

FIG. 3 also shows the phase lock circuitry 410, the oscillator 412 and the frequency divider 414 necessary to provide synchronized sampling and control with respect to standard signal frequencies. Many control systems utilize 400I-Iz as the carrier frequency and carrier modulation is usually of double side band suppressed carrier form. Thus, the conductor 416 is supplied with a 12.6V RMS 400Hz synchronization signal or the conductor 418 is supplied with a 6.3V RMS 400 Hz synchronization signal and the conductor 420 is the 400l-Iz synchronization signal return. As will be describedlater, these signals effect phase lock through the conductor 422 from the output of the frequency divider 414 and the output of the phase lock circuit at 424 is applied to the oscillator 412 to provide the necessary high frequency signal which, as divided down by the frequency divider 414 provides the necessary frequency divided signals at the conductors 426, 428, 430, 432, and 434 and, as well as at the conductors 436 and 438 to provide the necessary timing signals. The two signals at the conductors 436 and 438 are applied to a channel selector 440 having the previously mentioned signals at the output conductors 368 and 382 and, additionally, signals at the conductors 442 and 444, all of which will be described hereinafter. The timing system also includes gating circuits indicated generally by the reference characters 446 and 448, hereinafter described, to provide the inhibiting signals at the conductor 36, which are applied to the gates 364 and 366 of FIGS. 4 and 5 over the respective conductors 370 and 374, and a further inhibiting signal at the conductor 450 (FIG. 3), which controls the output control logic circuitry of FIGS. 4 and 5 at the conductors 452 and 454 respectively.

As described hereinbefore, the circuits of FIGS. 4 and 5 each have l5 x and y inputs and 15 z outputs or product outputs and the system, additionally, provides the two further x and y inputs to the input compensation control logic 224 of FIG. 2 and the two further product outputs from the circuit 156 of FIG. 2. In total, then, the system as shown in FIGS. 2-5 has 32 input pairs and 32 product outputs but the system as shown is capable of utilizing two further circuits according to FIGS. 4 and 5, making a total of 64 channels which can be accommodated, FIG. 2 showing three spare x input conductors at 456 and three spare y input conductors at 458 and three spare z or product output conductors 460 which are reserved for further control purposes if desired or necessary.

Thus, the sampling rate for the system shown in FIGS. 2-5 is 64 times the carrier frequency or, taking the specific example of the 400Hz carrier frequency, the frequency divider output at the conductor 426 in FIG. 3 is at 25.6K l-Iz.

Relevant portions of the timing circuitry are shown in FIG. 7 wherein it will be seen that the synchronizing input conductors 416, 418 and 420 are connected to the primary windings 470 of a coupling transformer whose secondary windings 472 is connected to the phase lock quadrature demodulator 474 whose output is parallel fed to amplifier integrator 476 and oscillator 478. Amplifier integrator 476 provides the proper bias to control the frequency and phase of oscillator 478. The frequency output of the oscillator at the conductor 480 is at 51.2 K Hz and is applied to the frequency dividing clock 482 which includes the bank of four binaries 484, 486, 488 and 490 connected as shown to provide the 25.6 K I-Iz timing signals at the conductor 426, the 12.8K I-lz output signal at the conductor 428, the 6.4 K Hz output signal at conductor 430 and the 3.2 K Hz output signal at the conductor 432. The output at the conductor 432 is connected to the clock 500 so that the binaries 502, 504 and 506 thereof produce a 1.6K I-lz output signal at the conductor 434, an 800 Hz signal at the conductor 436, and a 400Hz signal at the conductor 438. The timing diagrams for the outputs at the conductors 426, 428, 430, 432, 434, 436 and438 are shown in FIG. 8. Further, FIG. 8 shows the timing diagrams for the outputs of the conductors 368, 372, 442 and 444 as provided by the channel selector 440 of FIG. 3 and which are derived from the signals at the conductors 436 and 438.

Referring back to FIG. 7, it will be seen that the 40OH2 output signal from the clock 500 is applied to the NAND gate 508 and through the resistor 510 to the base electrode of the transistor switching device 512. The output of the NAND gate 508 at the conductor 514 is applied through the resistor 516 to the base electrode of the transistor switching device 518. Thus, the switching devices 512 and 518 are conducting 180 out of phase with respect to each other. The effect of demodulator amplifier 474 is to force the output at the conductor 520 to take the form shown in full line in FIG. 10, thus constraining the signal at the conductor 438 to be 90 out of phase (quadrature) with respect to the synchronizing signal 522 shown in FIG. which is derived from the secondary of transformer 472 shown in FIG. 7.

The 25.6K Hz signal at the conductor 426 is applied to two amplifiers 522 and 524, the former of which produces a 3 microsecond pulse at the trailing edge of each of the timing signal pulses as shown in FIG. 9, first two lines. The signals on the conductor 370 in FIG. 4, in conjunction with the signal at the conductor 368 produce 16 consecutive timing signals, the first two of which are indicated on the third and fourth lines of FIG. 9. The next 1-6 timing signals are of course produced by the circuit of FIG. 5 due to presence of the signal of the conductor 372 in conjunction with the signals at the conductor 374.

In FIG. 7, the amplifier 524 provides, at its output conductor 526, I8 microsecond pulses as shown by the sixth line of FIG. 9 and this input in turn is connected to the amplifier 528 so as to produce at its output conductor 430, the 13 microsecond duration pulses shown in the last line in FIG. 9. This signal is applied to the NAND gate 532 which is connected through the conductor 534 to the base electrode of the transistor switching device 536 to open this switch during the 13 microsecond duration of the pulses at the conductor 530', thereby producing the z inhibit pulses at the conductor 450 shown in the fifth line of FIG. 9. These inhibiting pulses allow, in their interpulse period, the product outputs to be obtained during the sampling periods t t,, etc. as are indicated by the dashed lines 538 and 540 in FIG. 9.

FIG. 6 illustrates in detail the circuits associated with the multiplier device to provide the buffer amplifier inputs thereto and the scale factor and offset corrections previously mentioned. In FIG. 6, the multiplexing device 290 and input control logic 60 of FIG. 4 are shown as a series of x, switches 540 whereas the combination of the multiplexer 290 and the y, input control logic are shown as a'series of switches 542. Also, in FIG. 6, the multiplexer 290 and output control logic 154 of FIG. 4 are illustrated as a series of switches 544, all for the sake of clarity. In FIG. 6, the amplifier 392 in combination with the capacitor546 constitutes a sample and hold circuit for the set twenty-third product and this amplifier in combination with the capacitor 546 is identical to the various sample and hold circuits, banks of which are indicated by the reference characters 548 and 550 in FIGS. 4 and 5 respectively. It will be recalled that the twenty-seventh product was reserved for scale factor correction and that the scale factor correction amplifier 394 was described in conjunction with FIG. 3 as controlling a variable resistor device 148. FIG. 6 illustrates that a convenient form for effecting this function is to apply the output at the conductor 396 of the amplifier 94 to the gate electrodes 552 and 554 of a dual MOSFET transistor with reverse drain-source connections whereby to effect the variation in the variation in the input to the amplifier 142.

The seventh time slot product which should be zero is applied, as described before, to the amplifier integrator 384 to slew the output of the multiplier 138 to the appropriate value corresponding to correction for whatever value at the reality occurs at the input at 376 to the amplifier 384. The correction value is updated with each clock cycle until the signal at 376 is zero.

It will also be recalled that mention was made of the fact that the multiplier circuit 138 could be provided with further compensating circuits. The x and y input leads 560 and 562 can be trimmed'out across the resistors 564 and 566 respectively as shown to obtain the requisite temperature stability but, if desired, these variable resistor elements could be replaced by an integrate and hold amplifier such as 384 utilized for offset correction and the appropriate x and y inputs associated therewith to effect the desired corrections as described in conjunction with FIG. 1.

The principles described in conjunction with FIGS.

1-10 represent a basis multi-multiplier system capable of performing accurate multiplication of many pairs of signals. In addition to this basic function, the system is capable of performing many additional functions by suitable operations upon the product outputs. andin this sense, the basic system is easily programmable by suitable connection to external circuitry so as to achieve great versatility for a wide range of computational problems or other functions. FIGS. 11- 14 illustrate some typical examples. I

In FIG. 1 l, the-manner in which a division operation may be performed by simple additional circuitry for one channel is shown. One channel of the multi-multiplier is illustrated diagrammatically at 600 in FIG. 11 and an additional amplifier integrator 602 and summing resistors R, and R are connected as shown to perform the division function indicated. The x input to the channel 600 is the analog or slowly varying signal it whereas the y input to the channel 600 is the output E of the amplifier integrator 602. On successive sampling cycles, the difference between the analog or slowly varying signal 2 and the product output of the channel 600 is caused to go to zero to yield the division function E=-lOZR ./XR

In FIG. 12, diagrammatic illustration of the manner in which accurate sine wave molulation may be obtained by the use of a low cost, low accuracy multiplier device is shown. In FIG. 12, the multiplying circuit 606 illustrates one channel of the basic multiplier system whereas the multiplier 608 represents an external or discrete low accuracy multiplier device which may have an accuracy, say, of 2 percent. In addition to the discrete multiplier 608, a negative integration circuit 610 and the summing resistors 612 and 614 are employed. The carrier signal, in phase with the sampling rate of the multi-multiplier, is applied at the terminal 616 as one input to the low accuracy multiplier 608 and the other input at the conductor 628 is the output of integrator 610. The analog modulating signal is applied at terminal 620 as one input to the summing resistor network through resistor 614 to the input of the integrating circuit 610. This action would result in an output signal at 628 changing amplitude in a direction of opposite polarity with respect to the polarity of the signal at terminal 620. The product of the resultant signal on conductor 628 and the 400 HZ reference at terminal 616 produces a low accuracy suppressed carrier amplitude modulated signal at conductor 618 which is coupled through capacitor 604 for the purpose of blocking the unwanted output offset dc level present on conductor 618. The desired modulated output signal is demodulated in the high accuracy channel 606 and multiplied by a precision dc reference at input conductor 624 so that the product output at conductor 626 is current summed through resistor 612 with the input signal through resistor614. As resistor 612 and 614 are of equal value, any difference in the magnitude of the current values will produce a non-zero voltage applied to the integrator 610. The integrator causes the magnitude of the modulated output at terminal 622 to change in the require direction to permit the demodulated signal voltage at conductor 626 to exactly equal the input signal voltage at terminal 620 upon subsequent sampling cycles. Therefore, the accuracy of the discrete multiplier is effectively reduced from its original value of 2.0 percent to the 0.2 percent accuracy of the basic multiplier channel. To give an example, assuming the gain of each circuit 606 and 608 to be 0. l the dc reference voltage at the conductor 624 to be I V, the input signal at the terminal 620 to be 5V, the 400 HZ carrier reference to be 7VRMS, and the corresponding peak amplitude of the modulated signal arbitrarily to be 5.5V, the output of the channel 606 will be -5.5V. Since this output is greater in magnitude than the 5V input, the resultant summation ls -5.V which forces the integrator 610 to ramp toward zero decreasing its output at the conductor 628 and hence to decrease the output of the channel 606 on the next cycle and ultimately to force the summation between the product at the conductor 626 and the signal at the terminal 620 to zero, thereby providing precision modulation despite the inherent accuracy of the device 608.

To illustrate the arrangement of FIG. 12 in greater detail as it relates to the system described in conjunction with FIG. 1, reference is to FIG. 13. In FIG. 13, the 400 I-IZ generator 630 which drives the clock 20 is shown and the sample and hold circuit 634 corresponding to channel 606 of FIG. 12 is also shown. The negative integrator 610 of FIG. 12 is provided by the amplifier integrator 636 in FIG. 13. Otherwise the system corresponds to that illustrated in FIG. 1.

FIG. 14 illustrates an embodiment of the invention particularly useful in the aerospace filed and represents a programmed computation system. At the conductors 640, 642 and 644 are three 400 Hz suppressed carrier modulated input signals of typical form representing conventional resolver chain outputs which are unsealed direction cosine signals in the form 'of sines and cosines of azimuth (X) and elevation (0) angles. The desired output signals of do form are identified at the output conductors 646, 648, 650 and 652.

In the system of FIG. 14, channels of the basic system are employed as indicated at 654, 656, 658, 660, 676, 684, 686, 688 and 690 and there are three external operational amplifiers required for performing the amplifier integrator functions indicated at 662, 678 and 692.

The fact that the input signals are unsealed is indicated by the terms (1+A) in each case and the inherent demodulation characteristics of the present system, where used to demodulate signals of a carrier frequency equal to the sampling frequency, is clearly indicated.

Thus, the two inputs at the conductors 642 and 644 are both demodulated in the channels 654 and 656 due to the 400 Hz sampling rate as described in conjunction with FIGS. 2-10. The other inputs to these two channels is the output at the conductor 674 from the amplifier integrator 662. Due to the face that the outputs of the channels 654 and 656 at the conductors 668 and 664 respectively are multiplied by themselves in the channels 658 and 660 to provide the cosx and sin x outputs at the'conductors 670 and 666. From the fundamental relationship sin x+cos FL these two signals are compared with the reference signal 1 in the amplifier integrator 662 whose output will then be forced, on subsequent sample cycles to yield the value l/[(l+A) cos 0], as indicated. The output conductors 650 and 652 are of course tied to the output conductors 668 and 664 and the second inputs to the two channels 658 and 660 likewise are provided by the conductors 669 and 665 at which the cosx and sinx signals appear.

The signal at the conductor 674 is also applied to the division circuit 683 which is similar to that described in conjunction with FIG. 11 where R,=R ,z=1.0 and Fl [(l+A)cos0]. The output of the amplifier integrator 678 is forced to the value [1+A) cos0 by virtue of the fact that the 1.0 reference input at the conductor 680 and the output of the channel 676 at the conductor 677 are connected, in the division mode, to the amplifier integrator 678 with its output at the conductor 682 in turn fed back as an input to the channel 676. As in the case of FIG. 11, the product of the output E of the amplifier integrator and the X input l/[ 1+A )cosO] is forced to equal the Z input at the conductor 680. Thus, Ex=l or E. l/= X, the necessary condition to provide the output 1+A) cost? at the conductor 682.

This signal is applied as an input to the channel 686 to derive the cos 0 term at the output conductor 698 and thus both at the input conductor 700 to the channel 690 and at the cost) output conductor 648. Similar to the foregoing description in connection with the channels 658 and 660, the channels 688 and 690 develop the sin and cos 6 terms respectively, the former by applying the sin 0 term at the output conductor 694 of the channel 684 as the other input at the conductor 696 to the channel 688 and the latter as described immediately above. Initially, the sin 0 and cos 6 terms may contain error signals but the appearance of these terms at the output conductors 702 and 704, summed with the l .0 reference input at the conductor 706 forces the signal at the output conductor 708 of the amplifier integrator 692, on subsequent sampling cycles, exactly to equal the error term 1/l+A and thereby to provide the precise sin() and cosO outputs.

What is claimed is: 1. In a computational system, the combination of: analog multiplier means for producing a product output in response to a pair of inputs thereto; multiplexing means for applying successive pairs of input signals to said analog multiplier means, said multiplexing means having a plurality of input terminals; demultiplexing means connected to said analog multiplier means and having a plurality of output terminals for providing successive products of said pairs of input signals; clock means for repetitively actuating said multiplexing means and said demultiplexing means to provide time-sharing usage of said analog multiplier means; holding means for receiving said products at said output terminals of the demultiplexing means; and compensating input means for applying reference signals to at least one pair of said input terminals, the product of which reference signals is a known value, that holding means associated with the product of such pair of reference signals being connected to said analog multiplier means for periodically adjusting the output thereof to. said known value when said reference signals are applied as inputs thereto. 2. In a computational system, the combination of: analog multiplier means for producing a product output in response to a pair of inputs thereto; multiplexing means for applying successive pairs of input signals to said analog multiplier means, said multiplexing means having a plurality of input terminals;

' demultiplexing means connected to said analog multiplier means and having a plurality of output terminals for providing successive products of said pairs of input signals;

clock means for repetitively actuating said multiplexing means and said demultiplexing means to provide time-sharing usage of said analog multiplier means;

compensating input means for applying reference signals to at least one pair of said input terminals of the multiplexing means, the product of which reference signals is a known value, and

means for periodically adjusting the output of said analog multiplier means to said known value when said reference signals are applied as inputs thereto.

3. In a computational system, the combination of:

analog multiplier means for producing a product output in response to a pair of inputs thereto;

multiplexing means for applying successive pairs vof input signals to said analog multiplier means, said multiplexing means having a plurality of input terminals;

demultiplexing means connected to said analog multiplier means and having a plurality of output terminals for providing successive products of said pairs of input signals; and

clock means for repetitively actuating said multiplexing means and said demultiplexing means to provide time-sharing usage of said analog multiplier means;

said analog multiplier means including an analog multiplier, scale factor amplifier means, and a compensating variable resistor connected between said analog multiplier and said scale factor amplifier means.

4. In a computational system as defined in claim 3 ineluding compensating input means for applying reference signals to a pair of said input terminals of the analog multiplier means, the product of which reference signals is a known value, and means for varying said resistor to produce said known value at the output of said scale factor amplifier means when said reference signals are applied as inputs to said analog multiplier.

5. In a computational system, the combination of:

analog multiplier means for producing a product output in response to a pair of inputs thereto;

multiplexing means for applying successive pairs of input signals to said analog multiplier means, said multiplexing means having a plurality of input terminals; I

demultiplexing means connected to said analog multiplier means and having a plurality of output terminals for providing successive products of said pairs of input signals;

clock means for repetitively actuating said multiplexing means and said demultiplexing means to provide time-sharing usage of said analog multiplier means;

an external multiplier having the output of said clock means and the output at one terminal of said demultiplexing means as inputs thereto and having an output terminal;

D.C. reference voltage means;

said output terminal of the external multiplier and said D.C. reference voltage means being connected as one pair of inputs to said multiplexing means;

a negative integrator connected to the output of said external multiplier and having an output terminal;

the output terminal of said negative integrator and the output terminal of said demultiplexing means corresponding to said one pair of inputs to said multiplexing means being connected as another pair of inputs to said multiplexing means; and

said another pair of inputs corresponding to said one terminal of the demultiplexing means, whereby the output of said external multiplier is a precisely modulated signal at the frequency of said clock means.

6. In a computational system, the combination of:

analog multiplier means for producing a product output in response to a pair of inputs thereto;

multiplexing means for applying successive pairs of input signals to said analog multiplier means, said multiplexing means having a plurality of input terminals;

demultiplexing means connected to said analog multiplier means and having a plurality of output terminals for providing successive products of said pairs of input signals;

clock means for repetitively actuating said multiplexing means and said demultiplexing means to provide time-sharing usage of said analog multiplier means; and

means for operating on the output signal of at least one output terminal of said demultiplexing means to provide an output other than said product of the corresponding pair of input signals to said multiplexing means.

7. As a basic building block of a programmable analog computer, the combination of:

at least one high accuracy analog multiplier means;

means for repetitively and successively applying input signal pairs as inputs to said multiplier means;

means for separating the output products of said analog multiplier means into discrete product signal outputs corresponding to the input signal pairs;

compensating means for periodically correcting the output of said analog multiplier means, said compensating means including means for applying a pair of reference signals, whose product is a fixed and known value, as an input signal pair to said multiplier means, and means connecting the corresponding product output signal to said multiplier means for causing its output to comply with said known value.

8. In a computational system, the combination of:

analog multiplier means for producing a product output in response to a pair of inputs thereto;

multiplexing means for applying successive pairs of input signals to said analog multiplier means, said multiplexing means having a plurality of input terminals;

demultiplexing means connected to said analog multiplier means and having a plurality of output terminals for providing successive products of said pairs of input signals;

clock means for repetitively actuating said multiplex-.

ing means and said demultiplexing means to provide time-sharing usage of said analog multiplier means;

means for applying at least some input signal pairs to said multiplexing means which are modulated signals of a selected carrier frequency; and

said clock means being slaved to said selected carrier frequency whereby the outputs of said demultiplexing means corresponding to said some input signal pairs are demodulated.

9. In a computational system as defined in claim 8 including holding means at each of the outputs of said demultiplexing means.

10. Ina computational system as defined in claim 9 including means operating on the outputs of at least one of said holding means or providing an output other 

1. In a computational system, the combination of: analog multiplier means for producing a product output in response to a pair of inputs thereto; multiplexing means for applying successive pairs of input signals to said analog multiplier means, said multiplexing means having a plurality of input terminals; demultiplexing means connected to said analog multiplier means and having a plurality of output terminals for providing successive products of said pairs of input signals; clock means for repetitively actuating said multiplexing means and said demultiplexing means to provide time-sharing usage of said analog multiplier means; holding means for receiving said products at said output terminals of the demultiplexing means; and compensating input means for applying reference signals to at least one pair of said input terminals, the product of which reference signals is a known value, that holding means associated with the product of such pair of reference signals being connected to said analog multiplier means for periodically adjusting the output thereof to said known value when said reference signals are applied as inputs thereto.
 2. In a computational system, the combination of: analog multiplier means for producing a product output in response to a pair of inputs thereto; multiplexing means for applying successive pairs of input signals to said analog multiplier means, said multiplexing means having a plurality of input terminals; demultiplexing means connected to said analog multiplier means and having a plurality of output terminals for providing successive products of said pairs of input signals; clock means for repetitively actuating said multiplexing means and said demultiplexing means to provide time-sharing usage of said analog multiplier means; compensating input means for applying reference signals to at least one pair of said input terminals of the multiplexing means, the product of which reference signals is a known value, and means for periodically adjusting the output of said analog multiplier means to said known value when said reference signals are applied as inputs thereto.
 3. In a computational system, the combination of: analog multiplier means for producing a product output in response to a pair of inputs thereto; multiplexing means for applying successive pairs of input signals to said analog multiplier means, said multiplexing means having a plurality of input terminals; demultiplexing means connected to said analog multiplier means and having a plurality of output terminals for providing successive products of said pairs of input signals; and clock means for repetitively actuating said multiplexing means and said demultiplexing means to provide time-sharing usage of said analog multiplier means; said analog multiplier means including an analog multiplier, scale factor amplifier means, and a compensating variable resistor connected between said analog multiplier and said scale factor amplifier means.
 4. In a computational system as defined in claim 3 including compensating input means for applying reference signals to a pair of said input terminals of the analog multiplier means, the product of which reference signals is a known value, and means for varying said resistor to produce said known value at the output of said scale factor amplifier means when said reference signals are applied as inputs to said analog multiplier.
 5. In a computational system, the combination of: analog multiplier means for producing a product output in response to a pair of inputs thereto; multiplexing means for applying successive pairs of input signals to said analog multiplier means, said multiplexing means having a plurality of input terminals; demultiplexing means connected to said analog multiplier means and having a plurality of output terminals for providing successive products of said pairs of input signals; clock means for repetitively actuating said multiplexing means and said demultiplexing means to provide time-sharing usage of said analog multiplier means; an external multiplier having the output of said clock means and the output at one terminal of said demultiplexing means as inputs thereto and having an output terminal; D.C. reference voltage means; said output terminal of the external multiplier and said D.C. reference voltage means being connected as one pair of inputs to said multiplexing means; a negative integrator connected to the output of said external multiplier and having an output terminal; the output terminal of said negative integrator and the output terminal of said demultiplexing means corresponding to said one pair of inputs to said multiplexing means being connected as another pair of inputs to said multiplexing means; and said another pair of inputs corresponding to said one terminal of the demultiplexing means, whereby the output of said external multiplier is a precisely modulated signal at the frequency of said clock means.
 6. In a computational system, the combination of: analog multiplier means for producing a product output in response to a pair of inputs thereto; multiplexing means for applying successive pairs of input signals to said analog multiplier means, said multiplexing means having a plurality of input terminals; demultiplexing means connected to said analog multiplier means and having a plurality of output terminals for providing successive products of said pairs of input signals; clock means for repetitively actuating said multiplexing means and said demultiplexing means to provide time-sharing usage of said analog multiplier means; and means for operating on the output signal of at least one output terminal of said demultiplexing means to provide an output other than said product of the corresponding pair of input signals to said multiplexing means.
 7. As a basic building block of a programmable analog computer, the combination of: at least one high accuracy analog multiPlier means; means for repetitively and successively applying input signal pairs as inputs to said multiplier means; means for separating the output products of said analog multiplier means into discrete product signal outputs corresponding to the input signal pairs; compensating means for periodically correcting the output of said analog multiplier means, said compensating means including means for applying a pair of reference signals, whose product is a fixed and known value, as an input signal pair to said multiplier means, and means connecting the corresponding product output signal to said multiplier means for causing its output to comply with said known value.
 8. In a computational system, the combination of: analog multiplier means for producing a product output in response to a pair of inputs thereto; multiplexing means for applying successive pairs of input signals to said analog multiplier means, said multiplexing means having a plurality of input terminals; demultiplexing means connected to said analog multiplier means and having a plurality of output terminals for providing successive products of said pairs of input signals; clock means for repetitively actuating said multiplexing means and said demultiplexing means to provide time-sharing usage of said analog multiplier means; means for applying at least some input signal pairs to said multiplexing means which are modulated signals of a selected carrier frequency; and said clock means being slaved to said selected carrier frequency whereby the outputs of said demultiplexing means corresponding to said some input signal pairs are demodulated.
 9. In a computational system as defined in claim 8 including holding means at each of the outputs of said demultiplexing means.
 10. In a computational system as defined in claim 9 including means operating on the outputs of at least one of said holding means for providing an output other than said product of the corresponding input signal pair.
 11. In a computational system as defined in claim 8 including means operating on at least one of said products for producing an output other than said product. 